But right now you have both a concurrent assignment outside the process: Qoutmay think that "but juan we gonna know the signal input and output in the code anyway" and you may be right BUT, since the shift register is combined with Subtractor part (for efficiency).There will be some of you that confused about the code( especially for beginner). A-Write a VHDL code to model Universal Shift Register. Either it must be driven sequentially by the process, or it is driven concurrently and can never be driven by the process. In this step we're gonna show you the input and output of the signals.
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